The present invention generally relates to a manufacturing method for semiconductor devices, and more particularly, to a manufacturing method for improving the electrical characteristic in the connection between the polycrystalline semiconductor thin film to be used for bipolar type or field effect type integrated circuit transistors and semiconductor regions including high density impurities formed in the single crystal (monocrystalline) semiconductor substrate.
In the bipolar type or field effect type semiconductor circuit, the usefulness of using polycrystalline semiconductors for creating miniaturized elements is well known. For example, in the field of silicon semiconductor bipolar technology, it has become a common practice to use polycrystalline silicon as a diffusion source for fine wirings (electrodes) or shallow junctions, and particularly, the polysilicon electrode lead-out as a means for forming an emitter region of fine planar dimensions suitable for high speed operation has become an indispensable technology.
As an example of an emitter in which arsenic is diffused from poly-silicon, there is proposed "Self-aligned Double Diffusion polysilicon technology" (K. Kikuchi et al. International Electron device meeting Technical Digest of Papers pp. 420-423, 1986). According to this technique, a shallow emitter of about 50 nanometer junction depth was obtained by subjecting arsenic with a dose amount of 1.times.10.sup.16 /cm.sup.2 implanted into a polysilicon layer of about 300 nanometer thickness to a heat treatment at 900.degree. C. for 30 minutes for thermal diffusion. Furthermore, as shown in FIG. 19, an emitter of about 180 nanometer junction depth was formed by using a similar polysilicon and diffusing arsenic implanted therein under conditions of heat treatment of a comparatively high temperature (1000.degree. C., 20 min.). On the other hand, it is shown in the prior art that since diffusion at a higher temperature and a longer time is required to form a deeper emitter, the semiconductor region, such as a base region having been already formed by the foregoing process, is consequently diffused too deeply, so that it becomes impossible to obtain a transistor structure suitable for high speed operation. More specifically, in the process using thermal diffusion at a comparatively higher temperature (1000.degree. C., 20 min.) for forming an emitter of 180 nanometer depth suitable for high speed operation, since the base region was formed beforehand by ion implanting such as boron, the depth of the base region becomes greater than 400 to 500 nanometer. For example, using a currently commercially available ion implanter, in the case of forming a p-type base region with such a minimum implant acceleration energy (for example, 25 KeV) that is most stable with a little fluctuation, the junction depth of the base becomes about 500 nanometer, and, since the depth of the emitter formed at that time is about 180 nanometer, a transistor of about 320 nanometer base width is formed. A typical collector cut-off frequency f.sub.T of a transistor of 320 nanometer base width is about 5 GHz. In order to manufacture a higher performance transistor of 10 GHz cut-off frequency f.sub.T, it is necessary for the base depth to be 100 to 200 nanometer. In order for this to occur, the target width of the emitter to be formed by the thermal diffusion from polysilicon should be about 300 nanometer or more, and, accordingly, a heat treatment at a very high temperature and for a long time will be required. However, the result of such a treatment is that the base depth becomes considerably deep. Thus, using this method, there is no possibility of realizing a transistor of 100 to 200 nanometer base width.
On the other hand, as an alternative method for forming emitter-base junctions, a method has been proposed of directly implanting ions such as arsenic ions into P-type bases. For example, as shown in FIG. 20, arsenic of 1.times.10.sup.16 /cm.sup.2 was directly ion implanted into polysilicon at an acceleration energy of 50 KeV, and subjected to a heat treatment at 1000.degree. C. The emitter depth after the heat treatment for 60 min. diffusion time (t=60 min.) was about 430 nanometer, the depth after a 20 min. diffusion time (t=20 min.) was about 260 nanometer, while the depth after no heat treatment, that is, immediately after implanting (t=0 min.), was about 100 nanometer. As shown in FIG. 19, although the emitter depth obtained by diffusing arsenic from polysilicon through the heat treatment of 1000.degree. C. and 20 min. was about 180 nanometer, the emitter depth obtained by directly ion implanting arsenic into silicon and subjecting to a heat treating under the same conditions as above, that is, 1000.degree. C. and 20 min., was about 260 nanometer, as shown in FIG. 20, which was 80 nanometer deeper than the emitter depth obtained by diffusing from polysilicon. In this case, since the total amount of the arsenic impurity in silicon becomes larger in the case of direct ion implanting, the emitter resistance can be advantageously reduced. Furthermore, in the case of forming an emitter through the direct ion implanting, with respect to the lead-out method for such as Al electrode, it has become a common practice to directly lead out metallic electrodes from each emitter surface without using electrodes of polycrystalline semiconductors as intermediate layers.
As shown in FIG. 19, an additional problem with the formation of an emitter by diffusion from polysilicon is the existence of a silicon oxide thin film (residual insulation film) naturally formed between a polysilicon layer and a single crystal (monocrystalline) silicon substrate. This natural oxide film grows to a thickness of less than about 2 nanometer when non-single-crystal (non-monocrystalline, for example, polycrystalline or amorphous) semiconductor thin film such as polysilicon or amorphous silicon is deposited. Due to the variation of this thickness, the diffusion depth for the emitter becomes unstable. Furthermore, when this oxidized film becomes thick, the series resistance of the emitter is increased, resulting in deterioration or fluctuation in the transistor characteristic.
This problem makes it more difficult to lead out an electrode of a non-single-crystal material such as polysilicon or amorphous silicon from the deep emitter formed by the ion implantation method as shown in FIG. 20. That is, when polysilicon is deposited on the surface of the silicon containing a high density of surface impurities such as arsenic, the natural oxide film grows thicker than when polysilicon is deposited on the surface of a silicon surface containing a lower density of surface impurities. Thus, the ohmic contact between the highly-doped emitter and the deposited polysilicon is further deteriorated, resulting in a rapid increase in the resistance of the emitter.
Accordingly, the first technical task to be attained is the removal of the instability due to the natural oxide film.
The second technical task of the present invention is to form a comparatively deep or comparatively shallow junction of a predetermined depth through a heat treatment using a comparatively low diffusion temperature or using a comparatively high temperature for a short time. If a homogeneous junction of a predetermined depth for such as an emitter and the like can be formed through a heat treatment using a comparatively low diffusion temperature or using a comparatively high temperature and a short time, a transistor structure of narrow base width having an excellent high speed characteristic can be realized. For example, in order to form an emitter of about 250 nanometer depth according to a method such as the one shown in FIG. 19, a high temperature heat treatment of 1000.degree. C. for about 20 min. is required, resulting in the base region formed simultaneously being diffused too deeply, so that a transistor structure suitable for high speed operation can not be realized.
Furthermore, using the conventional method mentioned above, there is the additional problem that a solid phase epitaxial growth of silicon in the polysilicon film realigns the polysilicon film with the silicon substrate, when the emitter diffusion from polysilicon is performed at 900.degree. C.
This phenomenon is reported in a paper by S. Ozono et. al. entitled "Redistribution of heavily doped Arsenic in Poly-Si Film on Single Silicon Substrate during its Solid Phase Epitaxial Growth", 177th Electrochemical Society Meeting, Abstract No. 378, 1990, pp. 569 to 570.
In instances where influences due to the silicon oxide film, process contamination, etching damage by plasma and the like are small at the boundary (interface) between the polysilicon electrode and the silicon substrate, it is known that, when arsenic in polysilicon is thermally diffused, a solid phase epitaxial growth of silicon aligned to the face orientation of the silicon substrate takes place and a re-crystallized silicon of about 200 nanometer height is formed. By the formation of the re-crystallized silicon, the depth of the emitter diffusion layer becomes shallower than in the case where no epitaxial growth takes place and the current gain of the emitter is reduced. In the case of the formation of a solid phase epitaxial layer, the reliability of the transistor is reduced as the emitter area increases.
Thus, the third technical task to be attained by the present invention is the prevention of the solid phase epitaxial growth upon heat treating the emitter.
In the trial fabrication for NPN transistors for 0.5 .mu.m Bi-CMOS, accompanying the low temperature trend of the CMOS process for accomplishing a high package density, both a diffusion furnace heat treatment at 800.degree. C. to 850.degree. C. or a heat treatment by the Rapid Thermal Annealing (RTA) at 1000.degree. C. to 1100.degree. C. are proposed as heat treatment for the emitter. In the heat treatments at 800.degree. C. to 850.degree. C., because of the existence of a residual insulation film (natural silicon oxide film) between the polysilicon thin film and the silicon single crystal substrate, the arsenic impurities forming the emitter can not be diffused from the polysilicon thin film, and therefore, it is necessary to diffuse arsenic by a heat treatment at a high temperature but for a short time, such as RTA or the like. The NPN transistors made on the trial basis under such conditions realize a high performance of 15 GHz f.sub.r at a collector-emitter breakdown voltage (BV.sub.ceo) of 6 V and an emitter-base breakdown voltage (BV.sub.ebo) of 3 V. The problems with such a process to be solved in the near future are in stabilizing the emitter diffusion since RTA has poor reproducibility and ensuring the emitter-base breakdown voltage is sufficiently larger than the power supply voltage, so as to insure reliability.
The inventors of the present invention proposed a basic idea on which the present invention is based in U.S. patent application Ser. No. 378,671 filed on Jul. 12, 1989, to solve the problems mentioned above. In that application, a method is disclosed for fabricating a semiconductor device which comprises the steps of providing a semiconductor substrate having a single crystalline semiconductor layer of a first conductivity type, forming a first semiconductive region of a second conductivity type in the single crystalline semiconductor layer, forming a dielectric film on the semiconductor substrate either prior to or after the formation of the first semiconductor region, making at least one opening in the dielectric film to expose the first semiconductive region, forming a first non-crystalline semiconductor film on the surface of the first semiconductive region in the opening, forming a second semiconductive region of the first conductivity type into the first semiconductive region by implanting an impurity of the first conductivity type through the first semiconductor film, forming a second non-crystalline semiconductor film on the first semiconductor film and incorporating an impurity of the first conductivity type into the second semiconductor film.